1. Field of the Invention
This invention relates to semiconductor memory sense circuits particularly to variable threshold transistor memory sense circuits.
2. Description of the Prior Art
A semiconductor memory includes a plurality of memory cells which are normally arranged in an array having rows and columns which are orthogonal to one another. A memory cell may contain one or two variable threshold transistors such as a metal nitride oxide semiconductor (MNOS) transistor. Information is written into and read out of the memory array by selecting the row and column pertaining to the desired memory cell with a row decoder and column decoder. To write information into a memory cell, voltages are placed across the variable threshold transistor to shift the threshold voltage of the transistor, for example, to a threshold voltage of -2 volts and =8 volts. The threshold voltage of the transistor or pair of transistors is read out by placing a predetermined voltage on the selected row of the memory cell which is coupled to the gates of the variable threshold transistors in the row. The voltage is normally selected to cause the variable threshold transistor to turn on or source follow if its threshold voltage is -2 volts and to remain off or to conduct a very small amount of current in the microamperes, if the threshold voltage is at -8 volts.
In the prior art, the current passing through the variable threshold transistor between the source and drain electrodes is detected or sensed by comparing it with the current passing through a reference load or through another variable threshold transistor which has a predetermined threshold voltage. The sense circuit normally used to compare the conductivities of two load elements is a cross-coupled latch which is initially set so that neither transistor in the latch conducts current. For example, a cross-coupled latch consisting of two P-channel enhancement load, field effect transistors initially has its source, drain and gate electrodes charged to the same voltage. At the appropriate time for sensing, the gate of the first transistor and the drain of the second transistor are coupled to one load element while the gate of the second transistor and the drain of the first are coupled to a second load element. As the two load elements conduct current, the gates of the two transistors drop in voltage from their precharged potential. The load element having the greatest conductivity will pull its gate of the first transistor, for example, to a lower potential first resulting in turning on the first transistor first which supplies current to its drain and the other load element tending to pull the voltage at the other load element positive. Since the gate of the second transistor is coupled to the drain of the first transistor, the gate is pulled positive tending to turn the second transistor off. The gate of the first transistor continues to drop in potential while the gate of the second transistor is charged up causing the cross-coupled pair of field effect transistors to latch in a stable state.
In a bi-stable or cross-coupled sense latch, no latching occurs until the voltage has dropped on one of the gates of the transistors in the sense latch sufficient to cause one of the transistors to conduct current. In a large array of memory cells, many variable threshold transistors are coupled together such as by their source electrodes in a column before coupling through a column decoder to one side of the latch which results in a large capacitance to be discharged by the selected memory cell. The large capacitance on one side of the latch results in longer times for the voltage to drop and hence longer times for the latch to stabilize.
In the cross-coupled latch, the gate to source voltage changes as the variable threshold transistor discharges the voltage on its source; the voltage discharges to the final gate to source voltage of a field effect transistor operating in the source follower mode. The variable threshold transistor utilized in a memory array may be a drain source protected structure wherein a non-memory region in the gate oxide over the drain and source exists with the memory dielectric region in between as described by J. R. Cricchi, F. C. Blaha, and M. D. Fitzpatrick in a paper entitled "The Drain Source Protected MNOS Memory Device And Memory Endurance", at the International Electron Devices Meeting sponsored by the IEEE, 1973. For a memory having the highest density, the minimum size variable threshold transistor geometry is often selected which results in a transistor with unoptimized conduction characteristics.
If a memory cell has two load elements wherein each load element is a variable threshold transistor then the currents drawn by the load elements are I.sub.ds1 and I.sub.ds2. The difference in current between the two load elements is .DELTA.I.sub.ds. The .DELTA.I.sub.ds is determined by the .DELTA.V.sub.th, the difference in threshold voltage. Ideally, a uniform parallel conductance shift should occur at all current values. This would make the current sensing independent of the non-memory portions of the memory transistor since it would be modulated solely by the change in V.sub.th, threshold voltage, in the memory region. This is desirable since variable threshold transistors in certain memories operate at larger current values during read operation. The final source voltage, V.sub.s, is never reached since charging or discharging of the latched transistors to their threshold voltage, V.sub.th, occurs first. Therefore, care was taken to utilize optimized devices which produce a uniform (parallel) conductance shift. If a parallel or uniform conductance shift is not achieved, even though the differential write cell is written to a .DELTA.V.sub.th state, improper detection can occur due to the small .DELTA.I.sub.ds source follower charging currents. The .DELTA.I.sub.ds source follower charging currents can be below the sensitivity of the sense latch. For optimized conductance characteristics it has been shown experimentally that .DELTA.V.sub.th of the variable threshold transistors in a memory cell must be greater than 0.5 volts to insure correct detection by a cross-coupled sense latch. Larger .DELTA.V.sub.th requires longer write times to shift the threshold voltage of each variable threshold transistor which is undesirable.
It is therefore desirable to provide a sense circuit which will detect the threshold state of a variable threshold transistor without requiring the capacitance associated with a column of variable threshold transistors to be discharged.
It is further desirable to provide an improved sense circuit which will detect smaller .DELTA.V.sub.th between two variable threshold transistors to require less writing time.
It is further desirable to provide a sense amplifier which will operate adequately without the need to optimize the geometry of the drain source protected memory device for the sense circuit.